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\begin{document}	

\begin{titlepage}

\thispagestyle{fancy}
\lhead{}
\chead{
\large{\textit{
Informatics and Mathematical Modelling\\
Technical University of Denmark}}}
\rhead{}
\rule{0pt}{50pt}
\vspace{3cm}

\begin{center}

 	\huge{\textbf{02207 : Advanced Digital Design Techniques}}\\
 	\vspace{1cm}
 	\huge{Lab 1: Exercise on Synthesis}\\
 	\vspace{1cm}
 	\huge{Group \textit{dt07}}\\
\end{center}

\vspace{4cm}

\begin{flushright}
	\LARGE{Markku Eerola (s053739)}\\
	\vspace{0.3cm}
	\LARGE{Rajesh Bachani (s061332)}\\
	\vspace{0.3cm}
	\LARGE{Josep Renard (s071158)}\\
\end{flushright}
\cfoot{\today}
\end{titlepage}

%\begin{abstract}
%\centering
%Abstract to be created.
%\end{abstract}

%-----------------------------------------------------------
\newpage 
\tableofcontents

\newpage 
\section{Introduction}

The goal of the exercise was to get familiar with the process of synthesis of digital circuits, using special tools for synthesis such as Design Vision. A register-level netlist containing a 24-bit adder is synthesized in the exercise, for different values of the clock time period. The reports concerning the timing constraints, area, power consumption etc. which are generated by the tool are documented in the report.

\subsection{Authors by Section}
\begin{itemize}
\item \textit{Markku Eerola} Behavioral description for the 24-bit adder, a testbench for the adder and the top-level netlist.
\item \textit{Josep Renard} Simulation of testbench with Modelsim (for different values of signals in testbench), behavioral description for the 24-bit register.
\item \textit{Rajesh Bachani} Synthesis with Design Vision and analysis of the results from synthesis.
\end{itemize}
\section{Behavioral Description for 24-bit Adder}

\subsection{VHDL code for the 24-bit Adder}
% Describe something about the adder %
The VHDL code for a simple 24-bit adder is provided below.\\ 

\lstinputlisting[frame=trbl]{../source/NBitAdder.vhdl}
\newpage
\subsection{Simulation with Modelsim}
The behavior of this adder is verified in Modelsim. Following is a testbench for the adder, and also a screenshot for the waveform from the values provided by the testbench.

\lstinputlisting[frame=trbl]{../source/tbnadder.vhdl}
\newpage
\begin{figure}[htp]
\centering
\includegraphics[width = 6in]{../source/wave.jpg}
\caption{Simulation of the 24-bit adder with Modelsim for the testbench shown}
\end{figure}

As we can see, the values of a, b and cin at the point of the yellow line are 34545, 8990 and 1. The resulting sum is shown as 43536, which is correct. Even for the other values in the testbench, we can verify the adder is working fine.

\section{Behavioral Description for 24-bit Register}

The VHDL code for a 24-bit register is provided below.\\ 

\lstinputlisting[frame=trbl]{../source/reg.vhdl}

\section{Top-Level Netlist from 24-bit Adder and 24-bit Register}
\label{sec:netlist}

The VHDL code for the top-level netlist described in the exercise sheet, is provided below.\\ 
\lstinputlisting[frame=trbl]{../source/addernetlist.vhdl}

\newpage
\section{Synthesis Results}

The synthesis of the top-level netlist described in section \ref{sec:netlist} is done using Design Vision by Synopsys. We have synthesized the netlist for three different sets of clock time periods, which are 0.5, 1.0 and 2.0 ns. For each of these time periods, we have synthesized the netlist with and without constraints for low power. In the end, we have commented on the results obtained from the data gathered.

The power constraints for low power are 1 uW and 1 pW for maximum dynamic power and maximum leakage power respectively. This is done by using the following two commands (as is also shown in the exercise sheet):\\

\begin{lstlisting}[frame=trbl]{}
set_max_dynamic_power 1
set_max_leakage_power 1
\end{lstlisting}
\vspace{0.5cm}
For the synthesis in which no constraints are put on power, the values are kept at 10 mW and 30 uW for maximum dynamic power and maximum leakage power respectively.\\

\begin{lstlisting}[frame=trbl]{}
set_max_dynamic_power 10 mW
set_max_leakage_power 30 uW
\end{lstlisting}
\vspace{0.5cm}

In the following subsections, we give the results and comments of the synthesis for both the above mentioned power constraints. In the next section, we give comments for the change in area and power with respect to the different clock periods.

\newpage
\subsection{Clock Time Period = 0.5 ns}
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters}	& \textbf{Values}		& \textbf{Comment}\\ \hline
Dynamic Power				&	5.91 mW				& MET\\ \hline
Leakage Power 			&	11.04 uW			& MET\\ \hline
Library Setup Time  & 0.08 ns				& - \\ \hline
Data Arrival Time		& 0.43 ns				& - \\ \hline
SLACK								& -0.01 ns			& VIOLATED \\ \hline
Combinational Area	& 2700 um^2			& - \\ \hline
Non-Combinational Area	& 1343 um^2	& - \\ \hline
SVT cells						& 403						& - \\ \hline
HVT cells						& 0							& - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 0.5 ns, normal power}
\label{tab:syn0.5.1}
\end{table}

Synthesis for low power:

\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters}	& \textbf{Values}		& \textbf{Comment}\\ \hline
Dynamic Power				&	5.29 mW				& VIOLATED\\ \hline
Leakage Power 			&	9.22 uW				& VIOLATED\\ \hline
Library Setup Time  & 0.08 ns				& - \\ \hline
Data Arrival Time		& 0.44 ns				& - \\ \hline
SLACK								& -0.02 ns			& VIOLATED \\ \hline
Combinational Area	& 2345 um^2			& - \\ \hline
Non-Combinational Area	& 1343 um^2	& - \\ \hline
SVT cells						& 377						& - \\ \hline
HVT cells						& 0							& - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 0.5 ns, low power}
\label{tab:syn0.5.2}
\end{table}

\newpage
\subsection{Clock Time Period = 1.0 ns}
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters}	& \textbf{Values}		& \textbf{Comment}\\ \hline
Dynamic Power				&	2.76 mW				& MET\\ \hline
Leakage Power 			&	11.25 uW			& MET\\ \hline
Library Setup Time  & 0.08 ns				& - \\ \hline
Data Arrival Time		& 0.89 ns				& - \\ \hline
SLACK								& 0.02 ns				& MET\\ \hline
Combinational Area	& 2335 um^2			& - \\ \hline
Non-Combinational Area	& 1343 um^2	& - \\ \hline
SVT cells						& 276						& - \\ \hline
HVT cells						& 0							& - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 1.0 ns, normal power}
\label{tab:syn1.0.1}
\end{table}

Synthesis for low power:

\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters}	& \textbf{Values}		& \textbf{Comment}\\ \hline
Dynamic Power				&	1.71 mW				& VIOLATED\\ \hline
Leakage Power 			&	2.98 uW				& VIOLATED\\ \hline
Library Setup Time  & 0.09 ns				& - \\ \hline
Data Arrival Time		& 0.90 ns				& - \\ \hline
SLACK								& 0.00 ns				& MET\\ \hline
Combinational Area	& 1089 um^2			& - \\ \hline
Non-Combinational Area	& 1343 um^2	& - \\ \hline
SVT cells						& 205						& - \\ \hline
HVT cells						& 0							& - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 1.0 ns, low power}
\label{tab:syn1.0.2}
\end{table}

\newpage
\subsection{Clock Time Period = 2.0 ns}
\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters}	& \textbf{Values}		& \textbf{Comment}\\ \hline
Dynamic Power				&	0.896 mW			& MET\\ \hline
Leakage Power 			&	3.51 uW				& MET \\ \hline
Library Setup Time  & 0.09 ns				& - \\ \hline
Data Arrival Time		& 1.87 ns				& - \\ \hline
SLACK								& 0.05 ns				& MET \\ \hline
Combinational Area	& 631 um^2			& - \\ \hline
Non-Combinational Area	& 1343 um^2	& - \\ \hline
SVT cells						& 97						& - \\ \hline
HVT cells						& 0							& - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 2.0 ns, normal power}
\label{tab:syn2.0.1}
\end{table}

Synthesis for low power:

\begin{table}[htbp]
\begin{center}
\begin{tabular}{|l|l|l|}
\hline
\textbf{Parameters}	& \textbf{Values}		& \textbf{Comment}\\ \hline
Dynamic Power				&	0.88 mW				& MET\\ \hline
Leakage Power 			&	3.17 uW				& VIOLATED\\ \hline
Library Setup Time  & 0.09 ns				& - \\ \hline
Data Arrival Time		& 1.91 ns				& - \\ \hline
SLACK								& 0.00 ns			& MET\\ \hline
Combinational Area	& 614 um^2			& - \\ \hline
Non-Combinational Area	& 1343 um^2	& - \\ \hline
SVT cells						& 97						& - \\ \hline
HVT cells						& 0							& - \\ \hline
\end{tabular}
\end{center}
\caption{Clock time-period 2.0 ns, low power}
\label{tab:syn2.0.2}
\end{table}

\newpage
\subsection{Comments}
Comments on synthesis results for low-power:
\begin{itemize}
\item For low power, the tool has tried to reduce the power to some extent. In some cases the constraint for the maximum dynamic power is met, while the constraint for maximum leakage power is never met.
\item The little reduction in the power with the low power constraints, is achieved by reducing the number of SVT cells in the design. This is because the SVT cells take more power as compared to the HVT cells. But since these cells are faster, reducing their number increases the delay in the circuit, as can be seen by an increase in the time of data arrival for all the three cases.
\item The combinational area reduces when synthesizing for low power. This can be explained with the reduction in the number of SVT cells.
\item We would have expected to see an increase in the number of HVT cells when synthesis is performed for low power, but it has not been the case. Of course, there is a reason for that. The number of SVT cells determined, are the ones on the critical path. Hence, no SVT cells from the critical path are replaced with HVT cells. Certain SVT cells are replaced with HVT cells, but outside the critical path.
\item For the clock time period of 2.0 ns, we note that there is no reduction in the number of SVT cells, when synthesized for low power. The reason for this is follows: for 2.0 ns, the circuit synthesized consists of sequential gates to perform the addition. In this case, there is very little scope of reducing the number of cells on the critical path, since the path is quite linear in flow. But the area is reduced very slightly, since some cells which are not on the critical path, are changed for low power.
\end{itemize}

\noindent Comments on variations observed by changing the clock time-period:
\begin{itemize}
\item The design is not synthesized successfully for the clock time period of 0.5 ns. The critical path in this case for the adder is 0.43 ns and adding the register setup and propagation delay time, the total time delay becomes greater than 0.5 ns. However, we see that the circuit is successfully synthesized for timing constraints of 1.0 ns and 2.0 ns.

\item The number of cells decreases with the increasing clock time period. So, as the constraint on the time period is reduced, the circuit is synthesized with lower number of cells. This is because the design is moving from parallel to sequential with an increase in clock time period constraint.

\item The area for the non-combinational circuit remains the same in all the cases. This is expected since the non-combinational circuit consists of three registers, which would have the same internal design on synthesis. The synthesis is mainly done for the internal design of the 24-bit adder, depending on the constraints of clock time period.

\item The area for the combinational circuit decreases with the increasing clock time period. This is because the number of cells decreases in the synthesized circuit.

\item The total power, including the dynamic power and the leakage power, decreases as the clocl time period is increased. Again, the reason for this is the decrease in the number of cells. 
\end{itemize}


\end{document}